Presentation | 2012/2/24 Satisfiability Verification of Constraints in System Development Using SysML TETSUSHI FUKUDA, KENJI HISAZUMI, AKIRA FUKUDA, |
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Abstract(in English) | SysML enables us to model hardware, software and humans related to systems comprehensively and SysML is expected to enable system design, analysis and verification. e constraints using requirement diagram and parametric diagram, but method to use the constrains in design and verify satisfiability of the constraints is not obvious. In this paper, we specify abstract constraints of requirement diagram using FMEA and identify constraints in design. Moreover, we propose a method to verify a satisfiability of the constraints using Yices, a SMT solver. |
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Paper # | Vol.2012-SLDM-155 No.12,Vo.2012-EMB-24 No.12 |
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Committee | DC |
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Conference Date | 2012/2/24(1days) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
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Title (in English) | Satisfiability Verification of Constraints in System Development Using SysML |
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1st Author's Name | TETSUSHI FUKUDA |
1st Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University() |
2nd Author's Name | KENJI HISAZUMI |
2nd Author's Affiliation | System LSI Research Center, Kyushu University |
3rd Author's Name | AKIRA FUKUDA |
3rd Author's Affiliation | Faculty of Information Science and Electrical Engineering, Kyushu University |
Date | 2012/2/24 |
Paper # | Vol.2012-SLDM-155 No.12,Vo.2012-EMB-24 No.12 |
Volume (vol) | vol.111 |
Number (no) | 462 |
Page | pp.pp.- |
#Pages | 6 |
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