Presentation | 2012/2/24 New optically reconfigurable gate array VLSI to enable a negative logic implementation Retsu Moriwaki, Minoru Watanabe, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Up to now, as one of multi-context devices, an optically reconfigurable gate array (ORGA) has been developed to achieve high-speed reconfiguration and to provide numerous reconfiguration contexts. For an acceleration method by reducing the number of bright bits, we have developed a new ORGA VLSI-chip. This paper presents reconfiguration acceleration results on the new ORGA-VLSI chip. |
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Paper # | VoL2012-SLDM-155 No.8,Vol.2012-EMB-24 No.8 |
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Committee | DC |
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Conference Date | 2012/2/24(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | New optically reconfigurable gate array VLSI to enable a negative logic implementation |
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1st Author's Name | Retsu Moriwaki |
1st Author's Affiliation | Shizuoka University Electric and Electronic Engineering() |
2nd Author's Name | Minoru Watanabe |
2nd Author's Affiliation | Shizuoka University Electric and Electronic Engineering |
Date | 2012/2/24 |
Paper # | VoL2012-SLDM-155 No.8,Vol.2012-EMB-24 No.8 |
Volume (vol) | vol.111 |
Number (no) | 462 |
Page | pp.pp.- |
#Pages | 5 |
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