| Presentation | 2012/2/24 Partial Redundant Fault Secure High Level Synthesis for RDR Architecture SHO TANAKA, MASAO YANAGISAWA, NOZOMU TOGAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As device feature size decreases, the reliability improvement against soft errors becomes quite necessary. A fault-secure system, in which concurrent error detection is realized, is one of the solutions to this problem. On the other hand, the average interconnect delay exceeds the gate delay which leads to the timing closure problem. By using regular-distributed-register architecture (RDR architecture), we can estimate interconnection delays very accurately and influence of their interconnect can be much reduced even in the behavioral level. In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for an RDR architecture. In fault-secure high-level synthesis, a recomputation CDFG a part of normal-computation CDFG must be scheduled and bound to functional units. Firstly, our algorithm re-uses vacant areas on RDR islands to allocate new function units additionally for the re-computation CDFG.Secondly, we propose a scheduling algorithm which minimize the number of insert comparator nodes. We show the effectiveness of the proposed algorithm through experimental results. Our algorithm reduces the soft error rate by an average of 57% compared with the non fault-secure approach. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | Vol.2012-SLDM-155 No.4,Vol.2012-EMB-24 No.4 |
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| Committee | DC |
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| Conference Date | 2012/2/24(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Partial Redundant Fault Secure High Level Synthesis for RDR Architecture |
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| 1st Author's Name | SHO TANAKA |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | MASAO YANAGISAWA |
| 2nd Author's Affiliation | Dept. of Electronic and Photonic Systems, Waseda University |
| 3rd Author's Name | NOZOMU TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2012/2/24 |
| Paper # | Vol.2012-SLDM-155 No.4,Vol.2012-EMB-24 No.4 |
| Volume (vol) | vol.111 |
| Number (no) | 462 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |