Presentation 2012/2/24
Fast and Exact Cache Configuration Simulation for Two-core L1 Cache
MASASHI TAWADA, MASAO YANAGISAWA, NOZOMU TOGAWA,
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Abstract(in English) Recently, multiple-core processors are used in embedded systems very often. Since application programs running are much limited on embedded systems, there must exist an optimal cache memory in terms of power and area. Simulating application programs on various cache configurations is one of the best options to determine the optimal cache configuration. Multicore cache configuration simulation, however, is much more complicated and takes much more time than single-core cache configuration simulation. In this paper, we propose a very fast two-core L1 cache configuration simulation algorithm. We first propose a new data structure where just a single data structure represents two or more multicore cache configurations with different cache associativities. After that, we propose a new multicore cache configuration simulation algorithm using our new data structure associated with new theorems.
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Paper # Vol.2012-SLDM-155 No.3,Vo.2012-EMB-24 No.3
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Conference Date 2012/2/24(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Fast and Exact Cache Configuration Simulation for Two-core L1 Cache
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1st Author's Name MASASHI TAWADA
1st Author's Affiliation Dept. of Computer Science and Engineering, Waseda University()
2nd Author's Name MASAO YANAGISAWA
2nd Author's Affiliation Dept. of Electronic and Photonic Systems, Waseda University
3rd Author's Name NOZOMU TOGAWA
3rd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
Date 2012/2/24
Paper # Vol.2012-SLDM-155 No.3,Vo.2012-EMB-24 No.3
Volume (vol) vol.111
Number (no) 462
Page pp.pp.-
#Pages 6
Date of Issue