| Presentation | 2012-03-06 Implementation of Tamper-Resistant Cryptographic DES Circuit using Dual-Rail RSL Memory Megumi SHIBATANI, Katsuhiko IWAI, Mitsuru SHIOZAKI, Shunsuke ASAGAWA, Takeshi FUJINO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, it has been pointed out that Differential Power Analysis (DPA), one of the Side-Channel Attack techniques, is a threat to cryptographic circuits which handle confidential information. Therefore, a LSI design with DPA resistance is required and many techniques are proposed. As a technique against DPA, we have proposed a Dual-Rail RSL Memory system, which occupies small chip area and has low power consumption. Using our technique on the cryptographic circuit, we can achieve DPA resistance. On the linear circuit, the correlation between power consumption and the circuit operation is eliminated by the random masking method, and on the nonlinear circuit the power consumption is uniformized by balancing on a memory circuit that performs a dual-rail complementary operation. The Dual-Rail RSL memory method, which had been applied to an AES circuit, is newly applied to DES circuit. The peripheral circuits such as decoders and sense amplifiers are improved to flexible layout so that SBoxes with various input-and-output bits can be customized. Furthermore, DES circuit using the Dual-Rail RSL memories as SBoxes is designed using 0.18μm CMOS process. In this paper we will introduce our approach mentioned above, and report the evaluated results of chip area and DPA resistance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Side-Channel Attack / DPA / AES / DES / Dual-Rail RSL Memory |
| Paper # | VLD2011-125 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2012/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Tamper-Resistant Cryptographic DES Circuit using Dual-Rail RSL Memory |
| Sub Title (in English) | |
| Keyword(1) | Side-Channel Attack |
| Keyword(2) | DPA |
| Keyword(3) | AES |
| Keyword(4) | DES |
| Keyword(5) | Dual-Rail RSL Memory |
| 1st Author's Name | Megumi SHIBATANI |
| 1st Author's Affiliation | Department of Science and Engineering, Ritsumeikan University() |
| 2nd Author's Name | Katsuhiko IWAI |
| 2nd Author's Affiliation | Graduate School of Science and Technology, Ritsumeikan University |
| 3rd Author's Name | Mitsuru SHIOZAKI |
| 3rd Author's Affiliation | Research Organization of Science and Engineering, Ritsumeikan University |
| 4th Author's Name | Shunsuke ASAGAWA |
| 4th Author's Affiliation | Department of Science and Engineering, Ritsumeikan University |
| 5th Author's Name | Takeshi FUJINO |
| 5th Author's Affiliation | Department of Science and Engineering, Ritsumeikan University |
| Date | 2012-03-06 |
| Paper # | VLD2011-125 |
| Volume (vol) | vol.111 |
| Number (no) | 450 |
| Page | pp.pp.- |
| #Pages | 6 |
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