Presentation	2012-03-08 A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique Masanori Furuta, Taichi Ogawa, Tetsuro Itakura,
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Abstract(in English)	An eight-channel time-interleaved ADC with individual reference voltage buffers is presented. Each channel consists of buffer amplifier and two successive approximation ADC (SAR ADC) in a pipeline configuration. The proposed architecture shares an amplifier between the voltage buffer and the residue amplifier. The amplifier sharing technique achieves better isolation between the individual channels while minimizing the additional circuit. Over one bit redundancy is implemented to compensate the process variation of the MOM capacitance. Fabricated in 65nm CMOS with an active area of 0.36mm^2, the prototype chip achieves a peak SNDR of 32.3dB(single-channel) at 60MS/s and 26dB(time-interleave) at 480MS/s sampling rate and has a power consumption of 6mW.
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Paper #	CAS2011-128,SIP2011-148,CS2011-120
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Committee	CAS
Conference Date	2012/3/1(1days)
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Registration To	Circuits and Systems (CAS)
Language	ENG
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Title (in English)	A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique
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1st Author's Name	Masanori Furuta
1st Author's Affiliation	Toshiba Corporation()
2nd Author's Name	Taichi Ogawa
2nd Author's Affiliation	Toshiba Corporation
3rd Author's Name	Tetsuro Itakura
3rd Author's Affiliation	Toshiba Corporation
Date	2012-03-08
Paper #	CAS2011-128,SIP2011-148,CS2011-120
Volume (vol)	vol.111
Number (no)	465
Page	pp.pp.-
#Pages	4
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