| Presentation | 2012-03-08 Hardware Model of Two-Dimensional Non-separable GenLOT for Video Processing Shintaro HARA, Yuya OTA, Shogo MURAMATSU, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, a hardware model of two-dimensional non-separable GenLOT for video processing and a permutation module for wavelet structure are proposed. Existing transforms such as the discrete cosine trnsform (DCT) and discrete wavelet transform (DWT) are not suitable for the expression of diagonal edges or textures because these transforms are separable. The directional GenLOT proposed in this laboratory is suitable for the expression because it is non-separable. However, there is a problem of the processing speed in the directional GenLOT. It is expected that the specific hardware is effective to solve this problem. Therefore, the authors proposed a hardware model of two-dimensional non-separable GenLOT, where the model is designed for a still image processing. This study suggests to extend the hardware model to video processing of two-dimensional non-separable GenLOT by the modifying the preceding model. In addition, a module for wavelet structure is also proposed. Finally, a part of the model is described by VHDL, and the speed and area are evaluated in order to show the significance of the proposed architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Non-separable GenLOT / DCT / DWT / FPGA |
| Paper # | CAS2011-114,SIP2011-134,CS2011-106 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2012/3/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Model of Two-Dimensional Non-separable GenLOT for Video Processing |
| Sub Title (in English) | |
| Keyword(1) | Non-separable GenLOT |
| Keyword(2) | DCT |
| Keyword(3) | DWT |
| Keyword(4) | FPGA |
| 1st Author's Name | Shintaro HARA |
| 1st Author's Affiliation | Dept. of Electrical & Electronic Engineering, Niigata University() |
| 2nd Author's Name | Yuya OTA |
| 2nd Author's Affiliation | Dept. of Electrical & Electronic Engineering, Niigata University |
| 3rd Author's Name | Shogo MURAMATSU |
| 3rd Author's Affiliation | Dept. of Electrical & Electronic Engineering, Niigata University |
| Date | 2012-03-08 |
| Paper # | CAS2011-114,SIP2011-134,CS2011-106 |
| Volume (vol) | vol.111 |
| Number (no) | 465 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |