Presentation 2012-03-01
An Implementation to FPGA with the ZIP encoder
Daichi KAWASAKI, Ryo MURAKAMI, Takuya KATAYAMA, Tomoaki KIMURA,
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Abstract(in English) We proposed ZIP encoder hardware on FPGA by using VHDL.Because, as for compression time of ZIP encoder by computer software, much time is needed. Thus, ZIP encoder in which a real-time operation is possible is required. In this paper, we implemented ZIP encoder hardware to FPGA, and it was confirmed that this hardware can be processed at high speed than the computer software.
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Keyword(in English) ZIP encoder / FPGA / Compress
Paper # SIS2011-56
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Conference Information
Committee SIS
Conference Date 2012/2/23(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Implementation to FPGA with the ZIP encoder
Sub Title (in English)
Keyword(1) ZIP encoder
Keyword(2) FPGA
Keyword(3) Compress
1st Author's Name Daichi KAWASAKI
1st Author's Affiliation Information and Computer Sciences, Faculty of Information Technology, Kanagawa Institute of Technology()
2nd Author's Name Ryo MURAKAMI
2nd Author's Affiliation Information and Computer Sciences, Faculty of Information Technology, Kanagawa Institute of Technology
3rd Author's Name Takuya KATAYAMA
3rd Author's Affiliation Information and Computer Sciences, Faculty of Information Technology, Kanagawa Institute of Technology
4th Author's Name Tomoaki KIMURA
4th Author's Affiliation Information and Computer Sciences, Faculty of Information Technology, Kanagawa Institute of Technology
Date 2012-03-01
Paper # SIS2011-56
Volume (vol) vol.111
Number (no) 457
Page pp.pp.-
#Pages 4
Date of Issue