| Presentation | 2012-01-26 Study of pattern area and reconfigurable logic circuit with DG/CNT transistor Takamichi HAYASHI, Shigeyoshi WATANABE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Pattern area for 2～6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and Carbon-Nano-Tube (DG and CNT) has been newly estimated. Pattern area and number of logic dependence on input number of logic circuit has been analyzed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MOS double gate transistor / CNT transistor / reconfigurable logic / logic circuit / pattern area |
| Paper # | VLD2011-119,CPSY2011-82,RECONF2011-78 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2012/1/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study of pattern area and reconfigurable logic circuit with DG/CNT transistor |
| Sub Title (in English) | |
| Keyword(1) | MOS double gate transistor |
| Keyword(2) | CNT transistor |
| Keyword(3) | reconfigurable logic |
| Keyword(4) | logic circuit |
| Keyword(5) | pattern area |
| 1st Author's Name | Takamichi HAYASHI |
| 1st Author's Affiliation | Department of Engineering Research, Shonan Institute of Technology() |
| 2nd Author's Name | Shigeyoshi WATANABE |
| 2nd Author's Affiliation | Department of Information Science, Shonan Institute of Technology |
| Date | 2012-01-26 |
| Paper # | VLD2011-119,CPSY2011-82,RECONF2011-78 |
| Volume (vol) | vol.111 |
| Number (no) | 398 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |