Presentation 2012-01-25
Architecture and Estimation of Reconfigurable Processor for Multimedia Processing
Asuka Hayashi, Shuu'ichirou YAMAMOTO, Hideo MAEJIMA,
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Abstract(in English) In recent years, the demand of the processor which can process at high speed and flexibly integer arithmetic and floating-point arithmetic for multimedia processing. Especially, the processor which can process integer processing and floating-point processing in a required situation is demanded. We intend to design a high flexible reconfigurable processor for multimedia processing. We developed a reconfigurable processor which switches from general integer arithmetic and Multiply-and-ACcumulation(MAC) to floating-point arithmetic by processing integer arithmetic and floating-point arithmetic at reconfigurable logic unit.
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Keyword(in English) Reconfigurable Processor / Multimedia Processing / MAC / IEEE 754
Paper # VLD2011-103,CPSY2011-66,RECONF2011-62
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Committee RECONF
Conference Date 2012/1/18(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Architecture and Estimation of Reconfigurable Processor for Multimedia Processing
Sub Title (in English)
Keyword(1) Reconfigurable Processor
Keyword(2) Multimedia Processing
Keyword(3) MAC
Keyword(4) IEEE 754
1st Author's Name Asuka Hayashi
1st Author's Affiliation Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology()
2nd Author's Name Shuu'ichirou YAMAMOTO
2nd Author's Affiliation Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology
3rd Author's Name Hideo MAEJIMA
3rd Author's Affiliation Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology
Date 2012-01-25
Paper # VLD2011-103,CPSY2011-66,RECONF2011-62
Volume (vol) vol.111
Number (no) 399
Page pp.pp.-
#Pages 4
Date of Issue