Presentation 2012-01-25
Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router
Takeo NAKAMURA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Kimiyoshi USAMI, Hideharu AMANO,
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Abstract(in English) We have proposed a multi-voltage variable-pipeline router in order to reduce power consumption of Network-on-Chip (NoC). In this paper, we evaluated energy overhead, operating frequency, and delay of three domain patterns for switching the power supply: component-level such as virtual channels, router-level, and router-cluster-level(router x4) domains. As a result, when the operating frequency is 386.5HMz, switching delay between Vdd_ and Vdd_ is within a single clock cycle. Their break-even times (BETs) are 26, 19, 17 cycle, respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Network-on-chip / Low Power / Processor / Variable pipline
Paper # VLD2011-99,CPSY2011-62,RECONF2011-58
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Committee RECONF
Conference Date 2012/1/18(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router
Sub Title (in English)
Keyword(1) Network-on-chip
Keyword(2) Low Power
Keyword(3) Processor
Keyword(4) Variable pipline
1st Author's Name Takeo NAKAMURA
1st Author's Affiliation Faculty of science and Technology, Keio University()
2nd Author's Name Hiroki MATSUTANI
2nd Author's Affiliation Faculty of science and Technology, Keio University
3rd Author's Name Michihiro KOIBUCHI
3rd Author's Affiliation National Institute of Informatics
4th Author's Name Kimiyoshi USAMI
4th Author's Affiliation Shibaura Institute of Technology
5th Author's Name Hideharu AMANO
5th Author's Affiliation Faculty of science and Technology, Keio University
Date 2012-01-25
Paper # VLD2011-99,CPSY2011-62,RECONF2011-58
Volume (vol) vol.111
Number (no) 399
Page pp.pp.-
#Pages 6
Date of Issue