Presentation 2012-01-25
Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications
Kotoko FUJITA, Nadav BERGSTEIN, Hakaru TAMUKOH, Masatoshi SEKINE,
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Abstract(in English) The implementation of TCP/IP is required for various embedded applications to connect into the Internet. However, software implementation with embedded CPU lacks the performance of processing speed and ASIC implementation is less in flexibility. In this paper, we propose an FPGA TCP/IP Stack. The hardware implementation of TCP/IP is directly connected to WEB application. In addition to previous works, we implement ICMP and TCP option including MSS, Window Scale and TimeStamp. Experimental results show that the proposed FPGA TCP/IP Stack achieves 95 Mbps actual performance, while the theoretical performance is 100 Mbps. Moreover, a WEB streaming demonstration system, which is constructed with the FPGA TCP/IP Stack and a circuit of video compression and extension, processes the image (VGA Full color) about 20fps and achieves 30 times improvement in calculation speed over the existing similar software implementation.
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Keyword(in English) TCP/IP / TOE / hw/sw complex system / FPGA / WEB application
Paper # VLD2011-91,CPSY2011-54,RECONF2011-50
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Conference Information
Committee RECONF
Conference Date 2012/1/18(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications
Sub Title (in English)
Keyword(1) TCP/IP
Keyword(2) TOE
Keyword(3) hw/sw complex system
Keyword(4) FPGA
Keyword(5) WEB application
1st Author's Name Kotoko FUJITA
1st Author's Affiliation Institute of Engineering, Tokyo Univ. of Agriculture and Technology()
2nd Author's Name Nadav BERGSTEIN
2nd Author's Affiliation Institute of Engineering, Tokyo Univ. of Agriculture and Technology
3rd Author's Name Hakaru TAMUKOH
3rd Author's Affiliation Institute of Engineering, Tokyo Univ. of Agriculture and Technology
4th Author's Name Masatoshi SEKINE
4th Author's Affiliation Institute of Engineering, Tokyo Univ. of Agriculture and Technology
Date 2012-01-25
Paper # VLD2011-91,CPSY2011-54,RECONF2011-50
Volume (vol) vol.111
Number (no) 399
Page pp.pp.-
#Pages 6
Date of Issue