Presentation 2012-02-13
An approach for adaptive determination of IDDQ testing criteria based on process parameter estimation
Michihiro SHINTANI, Takashi SATO,
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Abstract(in English) Miniaturization of LSI dimension causes parametric faults, in which fabricated chip does not satisfy its performance specification due to process variations. Under large process variations, leakage current should be tested thoroughly in addition to widely conducted delay fault testing. In this paper, we propose an approach that adaptively determines threshold current for IDDQ testing. In our method, process condition of a chip is first estimated using measured IDDQ currents. Then, upper bound of leakage current of the chip is estimated based on the estimated process condition. If an IDDQ current of the chip exceeds the bound, the chip is classified as fail. Through simulation experiments, we show effectiveness and challenges of the proposed threshold determination method.
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Keyword(in English) IDDQ Testing / Statistical Leakage Current Analysis / Process Parameter Estimation / Bayes' Theorem
Paper # DC2011-84
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Committee DC
Conference Date 2012/2/6(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An approach for adaptive determination of IDDQ testing criteria based on process parameter estimation
Sub Title (in English)
Keyword(1) IDDQ Testing
Keyword(2) Statistical Leakage Current Analysis
Keyword(3) Process Parameter Estimation
Keyword(4) Bayes' Theorem
1st Author's Name Michihiro SHINTANI
1st Author's Affiliation Graduate School of Informatics, Kyoto University()
2nd Author's Name Takashi SATO
2nd Author's Affiliation Graduate School of Informatics, Kyoto University
Date 2012-02-13
Paper # DC2011-84
Volume (vol) vol.111
Number (no) 435
Page pp.pp.-
#Pages 6
Date of Issue