Presentation 2012-02-13
A method to reduce shift-toggle rate for low power BIST
Takaaki KATO, Senling WANG, Kohei MIYASE, Yasuo SATO, Seiji KAJIHARA,
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Abstract(in English) Logic BIST using scan design has a problem with high power dissipation during test. In this work we propose a method that reduces shift-toggle rate of scan flip-flops for low power testing of the scan-BIST. The proposed method adds an extra circuit for reduction of the signal transition probability of pseudo random test patterns generated by an LFSR. In the experiment, we show shift-toggle rate and fault coverage of the test patterns generated by the proposed method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) BIST / scan test / low power dissipation / scan shift power
Paper # DC2011-80
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Committee DC
Conference Date 2012/2/6(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A method to reduce shift-toggle rate for low power BIST
Sub Title (in English)
Keyword(1) BIST
Keyword(2) scan test
Keyword(3) low power dissipation
Keyword(4) scan shift power
1st Author's Name Takaaki KATO
1st Author's Affiliation Department of Computer Science and Electronics Kyushu Institute of Technology:JST CREST()
2nd Author's Name Senling WANG
2nd Author's Affiliation Department of Computer Science and Electronics Kyushu Institute of Technology:JST CREST
3rd Author's Name Kohei MIYASE
3rd Author's Affiliation Department of Computer Science and Electronics Kyushu Institute of Technology:JST CREST
4th Author's Name Yasuo SATO
4th Author's Affiliation Department of Computer Science and Electronics Kyushu Institute of Technology:JST CREST
5th Author's Name Seiji KAJIHARA
5th Author's Affiliation Department of Computer Science and Electronics Kyushu Institute of Technology:JST CREST
Date 2012-02-13
Paper # DC2011-80
Volume (vol) vol.111
Number (no) 435
Page pp.pp.-
#Pages 5
Date of Issue