Presentation 2012-02-13
Note on Layout-Aware High Accuracy Estimation of Fault Coverage
Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki,
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Abstract(in English) Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. In this study, as one possible strategy to accurately estimate the defect level, we discuss on a fault coverage estimation with more accuracy for the given test pattern set. For each possible wire and wire pair in a given layout data, we execute critical area analysis multiple times, assuming different defect sizes. On the basis of critical areas obtained, we calculate weighted open/bridge fault coverages, considering frequency of occurrence of each fault.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) weighted bridge fault coverage / weighted open fault coverage / layout-aware / critical area
Paper # DC2011-79
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Committee DC
Conference Date 2012/2/6(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Note on Layout-Aware High Accuracy Estimation of Fault Coverage
Sub Title (in English)
Keyword(1) weighted bridge fault coverage
Keyword(2) weighted open fault coverage
Keyword(3) layout-aware
Keyword(4) critical area
1st Author's Name Masayuki Arai
1st Author's Affiliation Faculty of System Design, Tokyo Metropolitan University:Graduate School of System Design, Tokyo Metropolitan University()
2nd Author's Name Yoshihiro Shimizu
2nd Author's Affiliation / Faculty of System Design, Tokyo Metropolitan University:Graduate School of System Design, Tokyo Metropolitan University
3rd Author's Name Kazuhiko Iwasaki
3rd Author's Affiliation
Date 2012-02-13
Paper # DC2011-79
Volume (vol) vol.111
Number (no) 435
Page pp.pp.-
#Pages 6
Date of Issue