Presentation 2012-02-13
Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test
Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara,
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Abstract(in English) In this paper, we present to generate a test vector set to detect both transition and path delay faults. The proposed method detects the most path delay faults possible via transition delay tests without test data inflation. Experimental results for ITC'99 benchmark circuits demonstrate that the proposed method can detect many path delay faults in addition to transition delay faults with transition delay tests.
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Keyword(in English) Transition Delay Fault / Path Delay Fault / X-filling / X-identification / Test Generation
Paper # DC2011-78
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Committee DC
Conference Date 2012/2/6(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test
Sub Title (in English)
Keyword(1) Transition Delay Fault
Keyword(2) Path Delay Fault
Keyword(3) X-filling
Keyword(4) X-identification
Keyword(5) Test Generation
1st Author's Name Hiroaki Tanaka
1st Author's Affiliation Kyushu Institute of Technology()
2nd Author's Name Kohei Miyase
2nd Author's Affiliation Kyushu Institute of Technology
3rd Author's Name Kazunari Enokimoto
3rd Author's Affiliation Kyushu Institute of Technology
4th Author's Name Xiaoqing Wen
4th Author's Affiliation Kyushu Institute of Technology
5th Author's Name Seiji Kajihara
5th Author's Affiliation Kyushu Institute of Technology
Date 2012-02-13
Paper # DC2011-78
Volume (vol) vol.111
Number (no) 435
Page pp.pp.-
#Pages 6
Date of Issue