| Presentation | 2012-02-13 An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits Amy OGITA, Toshinori HOSOKAWA, Masayoshi YOSHIMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Companies which specialize in LSI designs and the marketing of products without manufacturing LSIs are called to "fabless". The business model that fabless companies design LSIs and foundry companies manufacture LSIs recently increases. Especially, the number of cases that LSI manufacturing is outsourced to foreign foundry companies increases. The outsourcing of LSI manufacturing to foreign foundry companies facilitates inserting Hardware Trojan circuits into LSIs. Hardware Trojan circuits are additional ones inserted into LSIs by attackers. The behavior of Hardware Trojan circuits expose products to the threat such as leakages of secret information, information falsification, and circuit destruction. In this paper, such a situation is assumed that LSI design partners insert Hardware Trojan circuits into design descriptions. LSI design partners are defined as other companies where fabless companies outsource parts of LSI designs. AES encryption circuits are targeted as the insertion of Hardware Trojan circuits. In this paper, we propose Hardware Trojan designs to leak a data relevant to an encryption key from AES encryption circuits and evaluate additional area overhead and toggle coverage compared with original circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | AES encryption circuits / hardware Trojan / security / design for testability |
| Paper # | DC2011-77 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2012/2/6(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits |
| Sub Title (in English) | |
| Keyword(1) | AES encryption circuits |
| Keyword(2) | hardware Trojan |
| Keyword(3) | security |
| Keyword(4) | design for testability |
| 1st Author's Name | Amy OGITA |
| 1st Author's Affiliation | Graduate School of Industrial Technology, Nihon University() |
| 2nd Author's Name | Toshinori HOSOKAWA |
| 2nd Author's Affiliation | College of Industrial Technology, Nihon University |
| 3rd Author's Name | Masayoshi YOSHIMURA |
| 3rd Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University |
| Date | 2012-02-13 |
| Paper # | DC2011-77 |
| Volume (vol) | vol.111 |
| Number (no) | 435 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |