Presentation 2012-02-13
Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection
Yoshihiro OHKAWA, Yukiya MIURA,
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Abstract(in English) Conventional edge triggered flip-flops sample a data signal synchronizing with single clock edge. If a noise signal occurs around the clock edge, flip-flops result in malfunction. Then, we have proposed dual edge triggered flip-flops to solve this problem. The FF has highly ability to prevent sampling a noise signal on a data line because it samples the data signal synchronizing with both of rising edge and falling edge. In this paper, we design a new circuit of the dual edge triggered flip-flops to improve circuit size, power consumption, and operation speed. In addition, we apply the dual edge triggered flip-flops to signal delay detection.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Edge triggered flip-flop / Clock edge / Noise / Synchronous circuits / Signal delay
Paper # DC2011-76
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Committee DC
Conference Date 2012/2/6(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection
Sub Title (in English)
Keyword(1) Edge triggered flip-flop
Keyword(2) Clock edge
Keyword(3) Noise
Keyword(4) Synchronous circuits
Keyword(5) Signal delay
1st Author's Name Yoshihiro OHKAWA
1st Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University()
2nd Author's Name Yukiya MIURA
2nd Author's Affiliation Faculty of System Design, Tokyo Metropolitan University
Date 2012-02-13
Paper # DC2011-76
Volume (vol) vol.111
Number (no) 435
Page pp.pp.-
#Pages 6
Date of Issue