Presentation 2012/1/12
Predicting the power consumption at Architectural-Level simulator
MITSUTAKA KIMURA, MAMORU TERAUCHI, TOSHIAKI KITAMURA,
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Abstract(in English) In order to reduce overall power consumption, architects need to consider power consumption from early stages of design processes. The aim of this study is to provide simple power consumption models that can be incorporated into cycle-level architecture simulators. A former related study did not conduct detailed power analyses on each module, but it treated each module as whether being operated or not. Designing a Content Addressable Memory (CAM) and evaluating power consumption in detail using SPICE, the authors have introduced a power evaluation function that shows how power consumption varies according to the data patterns. It has been confirmed that the proposed power estimation function provide detailed power consumption estimates that depend on compare results (HIT/MISS) of a CAM circuit, and that these estimates are quantitatively consistent with estimates obtained from SPICE simulation. The proposed power estimation function allows us to obtain more precise results than those based on a former study.
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Conference Date 2012/1/12(1days)
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Language JPN
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Title (in English) Predicting the power consumption at Architectural-Level simulator
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1st Author's Name MITSUTAKA KIMURA
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name MAMORU TERAUCHI
2nd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
3rd Author's Name TOSHIAKI KITAMURA
3rd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
Date 2012/1/12
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Volume (vol) vol.111
Number (no) 388
Page pp.pp.-
#Pages 7
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