Presentation 2012-01-19
Design of a High-Density and Low-Power Nonvolatile Logic Element Using MTJ Devices
Daisuke SUZUKI, Takahiro HANYU,
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Abstract(in English) A compact nonvolatile logic element (NVLE) using a magnetic-tunnel-junction (MTJ) and MOS-hybrid structure is proposed for a compact, low-power field-programmable gate array. The combination of an MTJ/MOS-hybrid structure and dynamic current-mode logic (DyCML) makes it possible to realize both logic function and storage function with a compact hardware. Moreover, the DyCML-based circuitry also makes it possible to perform a high-speed switching operation with low active-power dissipation. In fact, the proposed 4-input NVLE reduces transistor counts to 55% with the switching delay and he active power reduction to 83% and 64% respectively, compared to those of a conventional MTJ-based nonvolatile-SRAM-based implementation with a standby-power elimination capability during an idle phase.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Nonvolatile Logic-in-Memory Architecture / MTJ Device / FPGA / LE
Paper # ICD2011-135
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Conference Date 2012/1/12(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of a High-Density and Low-Power Nonvolatile Logic Element Using MTJ Devices
Sub Title (in English)
Keyword(1) Nonvolatile Logic-in-Memory Architecture
Keyword(2) MTJ Device
Keyword(3) FPGA
Keyword(4) LE
1st Author's Name Daisuke SUZUKI
1st Author's Affiliation Center for Spintronics Integrated Systems, Tohoku University:New Paradigm VLSI System Research Group, Tohoku University()
2nd Author's Name Takahiro HANYU
2nd Author's Affiliation Center for Spintronics Integrated Systems, Tohoku University:New Paradigm VLSI System Research Group, Tohoku University
Date 2012-01-19
Paper # ICD2011-135
Volume (vol) vol.111
Number (no) 388
Page pp.pp.-
#Pages 5
Date of Issue