| Presentation | 2012/1/12 データ保持性を利用したキャッシュのパワーゲーティング手法(低消費電力技術,集積回路とアーキテクチャの協創～ノーマリオフコンピューティングによる低消費電力化への挑戦～) , |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Caches consume large amount of leakage power because of their large area and massive transistors. To handle leakage power of caches, several works using power-gating(PG) was proposed. Even though PG is capable of high leakage saving, energy overhead by dismissing data is a big shortcoming of PG. In this paper, we focus on the data retentiveness of PG. This nature was not focused on previous works. Voltage of SRAM cell does not decrease to zero immediately after PG and this phenomenon is valuable to relive energy overhead for data recovery. We also propose a circuit to utilize data retentiveness. With the oracle knowledge control, we examined leakage saving potential of our proposal for L1 instruction and data cache. Results show that utilizing retentiveness of PG have big potential of leakage saving. |
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| Committee | ICD |
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| Conference Date | 2012/1/12(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
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| 1st Author's Affiliation | Tokyo University() |
| Date | 2012/1/12 |
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| Volume (vol) | vol.111 |
| Number (no) | 388 |
| Page | pp.pp.- |
| #Pages | 7 |
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