Presentation | 2011-12-15 A Implementation Technique of a Multibit Succesive Approximation Register AD Converter Naoya Kunikata, Toshimasa Matsuoka, Kenji Taniguchi, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A multibit SAR(Successive Approximation Register)-ADC is presented. Recent growth of the portable device market requires a low power and a high speed ADC. A SAR-ADC is suitable for low power applications, however the conversion speed is very slow. Multibit operation of SAR-ADC improves operation speed. The problem of multibit SAR-ADC is how to provide multiple reference voltages. In this study, an implementation technique of multibit SAR-ADC using capacitor efficient sub-DAC to provide multiple reference voltages is proposed. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | SAR-ADC / 4input comparator / multibit / ADC / high speed |
Paper # | ICD2011-107 |
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Committee | ICD |
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Conference Date | 2011/12/8(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Implementation Technique of a Multibit Succesive Approximation Register AD Converter |
Sub Title (in English) | |
Keyword(1) | SAR-ADC |
Keyword(2) | 4input comparator |
Keyword(3) | multibit |
Keyword(4) | ADC |
Keyword(5) | high speed |
1st Author's Name | Naoya Kunikata |
1st Author's Affiliation | Osaka University() |
2nd Author's Name | Toshimasa Matsuoka |
2nd Author's Affiliation | Osaka University |
3rd Author's Name | Kenji Taniguchi |
3rd Author's Affiliation | Osaka University |
Date | 2011-12-15 |
Paper # | ICD2011-107 |
Volume (vol) | vol.111 |
Number (no) | 352 |
Page | pp.pp.- |
#Pages | 5 |
Date of Issue |