Presentation | 2011-12-14 Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ota, Takao Ochiai, Masahiko Takenaka, Kouichi Itoh, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Physical Unclonable Functions (PUFs) are expected to represent an important solution for secure ID generation and authentication etc. In general, PUFs are considered to be more secure the larger their output entropy. However, the entropy of conventional PUFs is lower than the output bit length, because some output bits are random numbers, which are regarded as unnecessary for ID generation and discarded. We propose a novel PUF structure based on a Butterfly PUF with multiple RS latches, which generates larger entropy by utilizing location information of the RS latches generating random numbers. More specifically, while conventional PUFs generate binary values (0/1), the proposed PUF generates ternary values (0/1/random) in order to increase entropy. We estimate the entropy of the proposed PUF. According to our experiment with 40 FPGAs, a Butterfly PUF with 128 RS latches can improve entropy from 116 bits to 192.7 bits, this being maximized when the frequency of each ternary value is equal. We also show the appropriate RS latch structure for satisfying this condition, and validate it through an FPGA experiment. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | PUF / Butterfly PUF / RS latch / Metastable / Random number / FPGA / ID Generation / Authentication |
Paper # | ISEC2011-68 |
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Committee | ISEC |
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Conference Date | 2011/12/7(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Information Security (ISEC) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches |
Sub Title (in English) | |
Keyword(1) | PUF |
Keyword(2) | Butterfly PUF |
Keyword(3) | RS latch |
Keyword(4) | Metastable |
Keyword(5) | Random number |
Keyword(6) | FPGA |
Keyword(7) | ID Generation |
Keyword(8) | Authentication |
1st Author's Name | Dai Yamamoto |
1st Author's Affiliation | Fujitsu Laboratories Ltd.() |
2nd Author's Name | Kazuo Sakiyama |
2nd Author's Affiliation | The University of Electro-Communications |
3rd Author's Name | Mitsugu Iwamoto |
3rd Author's Affiliation | The University of Electro-Communications |
4th Author's Name | Kazuo Ota |
4th Author's Affiliation | The University of Electro-Communications |
5th Author's Name | Takao Ochiai |
5th Author's Affiliation | Fujitsu Laboratories Ltd. |
6th Author's Name | Masahiko Takenaka |
6th Author's Affiliation | Fujitsu Laboratories Ltd. |
7th Author's Name | Kouichi Itoh |
7th Author's Affiliation | Fujitsu Laboratories Ltd. |
Date | 2011-12-14 |
Paper # | ISEC2011-68 |
Volume (vol) | vol.111 |
Number (no) | 337 |
Page | pp.pp.- |
#Pages | 28 |
Date of Issue |