| Presentation | 2011-11-28 A configuration speed adjustment method on ORGAs Takashi YOZA, Minoru WATANABE, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, demands of implementing larger scale functions for an integrated circuit are increased. However, the progress of VLSI technologies is slowing down because current miniaturization of transistors is atomic scale. Therefore, optically reconfigurable gate arrays (ORGAs) that can realize dynamic reconfiguration have been developed as an alternative technology of current integrated circuits. The ORGAs consists of a holographic memory, a laser array, and a gate array VLSI. The ORGAs can be dynamically reconfigured by using such optical components. Under such conventional ORGAs, the worst-case reconfiguration time was applied for all configuration procedures although each configuration time is different from each other depending on the number of bright bits. So, the previous ORGA can not fully exploit its reconfiguration performance. Therefore, this paper proposes a configuration speed adjustment method on ORGAs to optimize each reconfiguration period. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Optically reconfigurable gate arrays / FPGAs / holographic memories / Reconfigurable devices |
| Paper # | RECONF2011-43 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2011/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A configuration speed adjustment method on ORGAs |
| Sub Title (in English) | |
| Keyword(1) | Optically reconfigurable gate arrays |
| Keyword(2) | FPGAs |
| Keyword(3) | holographic memories |
| Keyword(4) | Reconfigurable devices |
| 1st Author's Name | Takashi YOZA |
| 1st Author's Affiliation | Shizuoka University() |
| 2nd Author's Name | Minoru WATANABE |
| 2nd Author's Affiliation | Shizuoka University |
| Date | 2011-11-28 |
| Paper # | RECONF2011-43 |
| Volume (vol) | vol.111 |
| Number (no) | 323 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |