| Presentation | 2011-11-30 A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers Kazushige Kawai, Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi, Gensuke Goto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Three-dimensional (3-D) integration technologies are attractive for enhancing the speed of the arithmetic circuits. To implement 3-D stacked arithmetic units, effective circuit-partitioning strategies should be applied to exploit the potential of 3-D integration technologies. In this paper, we target a single-precision and a double-precision floating-point multipliers for speed-up the circuit2 by using 3-D integration. Our partitioning strategy is that the parts of the critical-path circuits for multiplication, normalizer and rounder are implemented on the same layer, avoiding to use TSV. The simulation analysis shows that the delay time reduces to 92% for a single-precision and 83% for a double-precision multipliers, as compared with those of the conventional 2-D floating-point multipliers |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 3-D integration / floating-point multiplier |
| Paper # | CPM2011-162,ICD2011-94 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2011/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers |
| Sub Title (in English) | |
| Keyword(1) | 3-D integration |
| Keyword(2) | floating-point multiplier |
| 1st Author's Name | Kazushige Kawai |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Yamagata University() |
| 2nd Author's Name | Jubee Tada |
| 2nd Author's Affiliation | Cyberscience Center, Tohoku University |
| 3rd Author's Name | Ryusuke Egawa |
| 3rd Author's Affiliation | Cyberscience Center, Tohoku University:JST CREST |
| 4th Author's Name | Hiroaki Kobayashi |
| 4th Author's Affiliation | Cyberscience Center, Tohoku University |
| 5th Author's Name | Gensuke Goto |
| 5th Author's Affiliation | Graduate School of Science and Engineering, Yamagata University |
| Date | 2011-11-30 |
| Paper # | CPM2011-162,ICD2011-94 |
| Volume (vol) | vol.111 |
| Number (no) | 327 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |