Presentation 2011-11-28
A Fast Transient Analysis of Linear Circuit using Quasi Zero Variance Importance Sampling
Tetsuro MIYAKAWA, Hiroshi TSUTSU, Hiroyuki OCHI, Takashi SATO,
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Abstract(in English) We propose a method to accelerate random walk based transient analysis of linear circuits. Our method uses quasi-zero-variance estimation with adaptive sample number determination, in which walk probabilities are adaptively updated to reduce estimation variance. The node voltages of previous time step are reused to give initial guesses for alternative probabilities at every time point, which reduces the total number of required samples. An adaptive determination of the number of samples makes estimation very stable and accelerate the analysis even further. The proposed analysis achieves more than 10x speedup against the conventional method.
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Keyword(in English) Voltage drop analysis / random-walk / importance sampling
Paper # VLD2011-64,DC2011-40
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Committee DC
Conference Date 2011/11/21(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Fast Transient Analysis of Linear Circuit using Quasi Zero Variance Importance Sampling
Sub Title (in English)
Keyword(1) Voltage drop analysis
Keyword(2) random-walk
Keyword(3) importance sampling
1st Author's Name Tetsuro MIYAKAWA
1st Author's Affiliation Graduate School of Informatics, Kyoto University()
2nd Author's Name Hiroshi TSUTSU
2nd Author's Affiliation Graduate School of Informatics, Kyoto University
3rd Author's Name Hiroyuki OCHI
3rd Author's Affiliation Graduate School of Informatics, Kyoto University
4th Author's Name Takashi SATO
4th Author's Affiliation Graduate School of Informatics, Kyoto University
Date 2011-11-28
Paper # VLD2011-64,DC2011-40
Volume (vol) vol.111
Number (no) 325
Page pp.pp.-
#Pages 6
Date of Issue