| Presentation | 2011-11-28 A Dynamically Configurable NoC Test Access Mechanism Takieddine SBIAI, Kazuteru NAMBA, Hideo ITO, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols...) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T^2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NoC / Test Access Mechanism / NoC reuse as TAM / Dynamically configured TAM |
| Paper # | VLD2011-60,DC2011-36 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2011/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Dynamically Configurable NoC Test Access Mechanism |
| Sub Title (in English) | |
| Keyword(1) | NoC |
| Keyword(2) | Test Access Mechanism |
| Keyword(3) | NoC reuse as TAM |
| Keyword(4) | Dynamically configured TAM |
| 1st Author's Name | Takieddine SBIAI |
| 1st Author's Affiliation | Graduate School of Advanced Integration Science, Chiba University() |
| 2nd Author's Name | Kazuteru NAMBA |
| 2nd Author's Affiliation | Graduate School of Advanced Integration Science, Chiba University |
| 3rd Author's Name | Hideo ITO |
| 3rd Author's Affiliation | Graduate School of Advanced Integration Science, Chiba University |
| Date | 2011-11-28 |
| Paper # | VLD2011-60,DC2011-36 |
| Volume (vol) | vol.111 |
| Number (no) | 325 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |