Presentation 2011-11-28
Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops
Shogo OKADA, Masaki MASUDA, Jun YAO, Hajime SHIMADA, Kazutoshi KOBAYASHI,
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Abstract(in English) Soft-error rates are becoming larger due to process scaling. Various ways of prediction for soft-error are being tried. In this paper, we measure power dissipation of two soft-error tolerant multiple-modular processors implemented with redundant and non-redundant flip-frops in 180nm, respectively. Redundant flip-flops have about 3x power and area than non-redundant flip-flops. The processor with redundant flip-flops has only 1.28x power and 1.71x area than the processor with non-redundant flip-flops.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Power / Area / Multiple Modular Processor / Redundant FF
Paper # VLD2011-59,DC2011-35
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Committee DC
Conference Date 2011/11/21(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops
Sub Title (in English)
Keyword(1) Power
Keyword(2) Area
Keyword(3) Multiple Modular Processor
Keyword(4) Redundant FF
1st Author's Name Shogo OKADA
1st Author's Affiliation Kyoto Institute of Technology()
2nd Author's Name Masaki MASUDA
2nd Author's Affiliation Kyoto Institute of Technology
3rd Author's Name Jun YAO
3rd Author's Affiliation Nara Institute of Science and Technology
4th Author's Name Hajime SHIMADA
4th Author's Affiliation Nara Institute of Science and Technology:JST,CREST
5th Author's Name Kazutoshi KOBAYASHI
5th Author's Affiliation Kyoto Institute of Technology:JST,CREST
Date 2011-11-28
Paper # VLD2011-59,DC2011-35
Volume (vol) vol.111
Number (no) 325
Page pp.pp.-
#Pages 6
Date of Issue