Presentation 2011-11-28
On Secure and Testable Scan Design Utilizing Shift Register Quasi-Equivalents
Katsuya FUJIWARA, Hideo FUJIWARA, Hideo TAMAMOTO,
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Abstract(in English) It is important to find an efficient design-for-testability methodology that satisfies both security and testability though there exists an inherent contradiction between security and testability for digital circuits. The authors reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and clarified each cardinality of several classes of shift register equivalents (SR-equivalents) as well as the whole class of SR-equivalents. In this paper, we introduce a wider class of circuits called "SR quasi-equivalents" that covers the class of SR-equivalents an still satisfies the testability and the testability and security similar to SR-equivalents. To estimate the security level, we clarify the cardinality of each equivalent class in SR-quasi-equivalents for several linear structured circuits.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Design for Testability / Secure Scan Design / Shift Register Equivalents / Shift Register Quasi-Equivalents / quivalent Class
Paper # VLD2011-54,DC2011-30
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Committee DC
Conference Date 2011/11/21(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On Secure and Testable Scan Design Utilizing Shift Register Quasi-Equivalents
Sub Title (in English)
Keyword(1) Design for Testability
Keyword(2) Secure Scan Design
Keyword(3) Shift Register Equivalents
Keyword(4) Shift Register Quasi-Equivalents
Keyword(5) quivalent Class
1st Author's Name Katsuya FUJIWARA
1st Author's Affiliation Department of Computer Science and Engineering, Akita University()
2nd Author's Name Hideo FUJIWARA
2nd Author's Affiliation Osaka Gakuin University
3rd Author's Name Hideo TAMAMOTO
3rd Author's Affiliation Department of Computer Science and Engineering, Akita University
Date 2011-11-28
Paper # VLD2011-54,DC2011-30
Volume (vol) vol.111
Number (no) 325
Page pp.pp.-
#Pages 6
Date of Issue