| Presentation | 2011-10-21 Receiver Front-End Design for CMOS High-Speed I/O Masaya KIBUNE, Hirotaka TAMURA, Takuji YAMAMOTO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Gbps-class CMOS transceivers for wire-line communication have the demand of the compatibility with wide variety of interface standards. This paper introduces the digital receiver architectures, which have lots of benefits of the scalability for both data rate and technology, and shows some techniques to reduce their size and power consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS / High-Speed I/O / Digital Receiver / CDR / Equalization |
| Paper # | CAS2011-56,NLP2011-83 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2011/10/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Receiver Front-End Design for CMOS High-Speed I/O |
| Sub Title (in English) | |
| Keyword(1) | CMOS |
| Keyword(2) | High-Speed I/O |
| Keyword(3) | Digital Receiver |
| Keyword(4) | CDR |
| Keyword(5) | Equalization |
| 1st Author's Name | Masaya KIBUNE |
| 1st Author's Affiliation | FUJITSU LABORATORIES LTD.() |
| 2nd Author's Name | Hirotaka TAMURA |
| 2nd Author's Affiliation | FUJITSU LABORATORIES LTD. |
| 3rd Author's Name | Takuji YAMAMOTO |
| 3rd Author's Affiliation | FUJITSU LABORATORIES LTD. |
| Date | 2011-10-21 |
| Paper # | CAS2011-56,NLP2011-83 |
| Volume (vol) | vol.111 |
| Number (no) | 243 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |