講演名 2011-09-26
MSA : Mixed Stochastic Algorithm for Placement with Larger Solution Space
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抄録(和)
抄録(英) The optimization techniques for VLSI/PCB placement with larger solution space and more objectives are facing big challenges to get a better solution with less runtime. In this paper, a new stochastic algorithm, named MSA, is proposed to improve the best case and the worst case of multi-objective placement. MSA is mixed by simulated annealing (SA), genetic algorithm (GA) and relay-race algorithm (RRA). It is based on a two-stage SA in which the temperature scheduling and a set of moving methods are designed differently for different stages, i.e. one type of relay. During the first stage, to explore huge solution space more effectively, the moving methods with big changes, such as the crossover operator from GA, are used in higher temperature. During the second stage, to get a better final convergence, the moving methods with small changes are used in lower temperature. Furthermore, the guide from RRA, i.e. another type of relay, which adjusts the selection probability among moving methods according to the improving speed, is integrated to improve the exploration efficiency. Based on the experiment comparing with the published data, MSA improves the multiple objectives of placement. MSA obtains >13% Pareto improvement for power with a constraint of delay, comparing with SA. Under a tight delay constraint, MSA outperforms RRA in a part of Pareto frontiers. Besides, a near log-linear trend of average improvement rates from SA to MSA is gotten. That means MSA is more suitable for the placement with larger solution space.
キーワード(和)
キーワード(英) optimization technique / physical design / stochastic algorithms / CAD technique / low power design
資料番号 VLD2011-42
発行日

研究会情報
研究会 VLD
開催期間 2011/9/19(から1日開催)
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開催地(英)
テーマ(和)
テーマ(英)
委員長氏名(和)
委員長氏名(英)
副委員長氏名(和)
副委員長氏名(英)
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幹事補佐氏名(英)

講演論文情報詳細
申込み研究会 VLSI Design Technologies (VLD)
本文の言語 ENG
タイトル(和)
サブタイトル(和)
タイトル(英) MSA : Mixed Stochastic Algorithm for Placement with Larger Solution Space
サブタイトル(和)
キーワード(1)(和/英) / optimization technique
第 1 著者 氏名(和/英) / Yiqiang SHENG
第 1 著者 所属(和/英)
Department of Communication and Integrated Systems, Tokyo Institute of Technology
発表年月日 2011-09-26
資料番号 VLD2011-42
巻番号(vol) vol.111
号番号(no) 216
ページ範囲 pp.-
ページ数 6
発行日