| Presentation | 2011-10-25 Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi TAKATA, Tohru ISHIHARA, Koji INOUE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given multiple tasks running on a single core processor. It reduces the energy consumption in a set-associative cache by activating only a single cache way at a time and deactivating the remaining cache ways. The technique also reduces the number of cache misses by changing the code placement in a main memory, which results in a reduction of the energy consumption in the main memory as well as the reduction of total execution time. Experiments using a commercial embedded processor demonstrate that the technique reduces the total energy consumption in the target processor system by 17% at the best case compared to the energy of the system which does not apply our technique. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | embedded system / multi task / cache memory |
| Paper # | SIP2011-76,ICD2011-79,IE2011-75 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2011/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption |
| Sub Title (in English) | |
| Keyword(1) | embedded system |
| Keyword(2) | multi task |
| Keyword(3) | cache memory |
| 1st Author's Name | Junshi TAKATA |
| 1st Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University() |
| 2nd Author's Name | Tohru ISHIHARA |
| 2nd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 3rd Author's Name | Koji INOUE |
| 3rd Author's Affiliation | Faculty of Information Science and Electrical Engineering, Kyushu University |
| Date | 2011-10-25 |
| Paper # | SIP2011-76,ICD2011-79,IE2011-75 |
| Volume (vol) | vol.111 |
| Number (no) | 258 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |