| Presentation | 2011-10-25 Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors Yosuke OHBAYASHI, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Accelerator cores in low-power heterogeneous multicore processors have multiple memory modules to increase the data access speed and to enable parallel data access. Recent low-power processors contain address generation units (AGUs) for fast address generation. To reduce the core-area, small functional units such as adders and counters are used in AGUs. Such small functional units make it difficult to implement complex addressing patterns without duplicating the data among multiple memory modules. The data-duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to remove the memory duplication and to increase the degree of parallelism. To verify the effectiveness of this method, we use window-based media processing which is widely used in many applications. According to the evaluation, the proposed method reduces the total processing time by 14% to more than 85% compared to the previous works. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Heterogeneous multicore / memory allocation / dynamic reconfiguration / multi-context FPGA |
| Paper # | SIP2011-74,ICD2011-77,IE2011-73 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2011/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors |
| Sub Title (in English) | |
| Keyword(1) | Heterogeneous multicore |
| Keyword(2) | memory allocation |
| Keyword(3) | dynamic reconfiguration |
| Keyword(4) | multi-context FPGA |
| 1st Author's Name | Yosuke OHBAYASHI |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Hasitha Muthumala WAIDYASOORIYA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Masanori HARIYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 4th Author's Name | Michitaka KAMEYAMA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2011-10-25 |
| Paper # | SIP2011-74,ICD2011-77,IE2011-73 |
| Volume (vol) | vol.111 |
| Number (no) | 258 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |