Presentation 2011-10-25
FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators
Yasuhiro TAKEI, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-efficient computing for various areas such as media processing and high-performance computing. It is important to explore the suitable architecture for each application since the suitable architectures are different from application to application. This paper reports an FPGA implementation of a heterogeneous multicore architecture with a MIMD-2D-type accelerator where independently-controlled ALUs are aligned in a 2-dimensional array.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) heterogeneous multicore processor / dynamically reconfiguration / FPGA / memory allocation
Paper # SIP2011-73,ICD2011-76,IE2011-72
Date of Issue

Conference Information
Committee ICD
Conference Date 2011/10/17(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators
Sub Title (in English)
Keyword(1) heterogeneous multicore processor
Keyword(2) dynamically reconfiguration
Keyword(3) FPGA
Keyword(4) memory allocation
1st Author's Name Yasuhiro TAKEI
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Hasitha Muthumala WAIDYASOORIYA
2nd Author's Affiliation Graduate School of Information Sciences, Tohoku University
3rd Author's Name Masanori HARIYAMA
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
4th Author's Name Michitaka KAMEYAMA
4th Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2011-10-25
Paper # SIP2011-73,ICD2011-76,IE2011-72
Volume (vol) vol.111
Number (no) 258
Page pp.pp.-
#Pages 4
Date of Issue