Presentation | 2011-10-24 残差信号アクセラレータによるH.264 CABAC復号器の高速化(プロセッサ,DSP,画像処理技術及び一般) Gen FUJITA, Kenji WATANABE, Toru HOMEMOTO, Ryoji HASHIMOTO, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This report presents a VLSI architecture of CABAC decoder for H.264/AVC. It adopts a multi-bin arithmetic decoder and reduces delay time by using parallel arithmetic execution module and binary stream buffering. The proposed architecture can decode an average of 1.42 bins / cycle, and be operated at a maximum frequency of 394MHz@40nm technology. As a result of the simulation, the real-time processing of 4K(4,096x2,048@30fps) video sequences is achieved. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | H.264 / decoder / CABAC / VLSI |
Paper # | SIP2011-67,ICD2011-70,IE2011-66 |
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Committee | ICD |
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Conference Date | 2011/10/17(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
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Keyword(1) | H.264 |
Keyword(2) | decoder |
Keyword(3) | CABAC |
Keyword(4) | VLSI |
1st Author's Name | Gen FUJITA |
1st Author's Affiliation | Dept. Engineering Informatics, Osaka Communication-Ellectro University() |
2nd Author's Name | Kenji WATANABE |
2nd Author's Affiliation | Synthesis Corporation |
3rd Author's Name | Toru HOMEMOTO |
3rd Author's Affiliation | Graduate School of Information Sience and Technology, Osaka University |
4th Author's Name | Ryoji HASHIMOTO |
4th Author's Affiliation | Graduate School of Information Sience and Technology, Osaka University |
Date | 2011-10-24 |
Paper # | SIP2011-67,ICD2011-70,IE2011-66 |
Volume (vol) | vol.111 |
Number (no) | 258 |
Page | pp.pp.- |
#Pages | 5 |
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