| Presentation | 2011-10-24 An H.264 Full HD 60i Double Speed Encoder IP Supporting Both MBAFF and Field-Pic Structure Akira MORIYA, Hajime MATSUI, Takaya OGAWA, Atsushi MOCHIZUKI, Sho KODAMA, Kazuyo KANOU, Hiromitsu NAKAYAMA, Shinichiro KOTO, Shunichi ISHIWATA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | HD video sequences are widely used in today's multimedia systems and many of these are encoded with H.264 codec. However, it is still challenging to develop a high-performance H.264 encoder because the H.264 encoding process needs a large amount of computations and memory accesses. In this paper, a novel H.264 encoder is described. This encoder can encode video sequences of full HD 60i at double speed. Both MBAFF and Field-Pic structure are supported as coding tool for interlaced video sequences. The memory bandwidths are reduced by using a hierarchical motion estimation method and a pipeline configuration with consideration of MBAFF. The encoder is implemented with 1637K logic gates and 336.5KB on-chip SRAM in the 65nm CMOS technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | H.264 / MBAFF / Field-Pic Structure / Full HD / Double Speed Encoder |
| Paper # | SIP2011-66,ICD2011-69,IE2011-65 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2011/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An H.264 Full HD 60i Double Speed Encoder IP Supporting Both MBAFF and Field-Pic Structure |
| Sub Title (in English) | |
| Keyword(1) | H.264 |
| Keyword(2) | MBAFF |
| Keyword(3) | Field-Pic Structure |
| Keyword(4) | Full HD |
| Keyword(5) | Double Speed Encoder |
| 1st Author's Name | Akira MORIYA |
| 1st Author's Affiliation | Center for Semiconductor Research & Development, Semiconductor & Storage Products Company, Toshiba Corporation() |
| 2nd Author's Name | Hajime MATSUI |
| 2nd Author's Affiliation | Center for Semiconductor Research & Development, Semiconductor & Storage Products Company, Toshiba Corporation |
| 3rd Author's Name | Takaya OGAWA |
| 3rd Author's Affiliation | Center for Semiconductor Research & Development, Semiconductor & Storage Products Company, Toshiba Corporation |
| 4th Author's Name | Atsushi MOCHIZUKI |
| 4th Author's Affiliation | Center for Semiconductor Research & Development, Semiconductor & Storage Products Company, Toshiba Corporation |
| 5th Author's Name | Sho KODAMA |
| 5th Author's Affiliation | Center for Semiconductor Research & Development, Semiconductor & Storage Products Company, Toshiba Corporation |
| 6th Author's Name | Kazuyo KANOU |
| 6th Author's Affiliation | Center for Semiconductor Research & Development, Semiconductor & Storage Products Company, Toshiba Corporation |
| 7th Author's Name | Hiromitsu NAKAYAMA |
| 7th Author's Affiliation | Logic LSI Division, Semiconductor & Storage Products Company, Toshiba Corporation |
| 8th Author's Name | Shinichiro KOTO |
| 8th Author's Affiliation | Research & Development Center Toshiba Corporation |
| 9th Author's Name | Shunichi ISHIWATA |
| 9th Author's Affiliation | Center for Semiconductor Research & Development, Semiconductor & Storage Products Company, Toshiba Corporation |
| Date | 2011-10-24 |
| Paper # | SIP2011-66,ICD2011-69,IE2011-65 |
| Volume (vol) | vol.111 |
| Number (no) | 258 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |