| Presentation | 2011-10-24 Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika FUJIOKA, Sho TAKIZAWA, Michitaka KAMEYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration memory for dynamically reconfigurable VLSI processors greatly reduced. Configuration memory reduction in the conventional dynamically reconfigurable parallel VLSI processor can be achieved based on semi-autonomous packet routing, where both autonomous packet data transfer and offline scheduling/allocation are effectively utilized. Dynamic reconfiguration of local memories is also introduced to utilize the control memory resources. According to requirement of the local memory capacity for each PE, partial crossbar switches are controlled by the packet destination address information. It is demonstrated that the packet-routing control storage capacity can be reduced to about 1/10 in some parallel processing example compared to the conventional dynamically reconfigurable VLSI. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | coarse-grain reconfigurable VLSI processor / semi-autonomous packet routing / dynamic reconfiguration of local memories / configuration memory |
| Paper # | SIP2011-64,ICD2011-67,IE2011-63 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2011/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer |
| Sub Title (in English) | |
| Keyword(1) | coarse-grain reconfigurable VLSI processor |
| Keyword(2) | semi-autonomous packet routing |
| Keyword(3) | dynamic reconfiguration of local memories |
| Keyword(4) | configuration memory |
| 1st Author's Name | Yoshichika FUJIOKA |
| 1st Author's Affiliation | Faculty of Engineering, Hachinohe Institute of Technology() |
| 2nd Author's Name | Sho TAKIZAWA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Michitaka KAMEYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2011-10-24 |
| Paper # | SIP2011-64,ICD2011-67,IE2011-63 |
| Volume (vol) | vol.111 |
| Number (no) | 258 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |