| Presentation | 2011-10-20 Fast Simulation of Multiconductor System with Nonlinear Devices by Using Block-Latency Insertion Method and Reduced Order Model Tadatoshi SEKINE, Hideki ASAI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a fast circuit simulation technique based on the block-latency insertion method (block-LIM) and a model order reduction (MOR) technique. The block-LIM is one of the efficient transient analysis methods adopting an explicit leapfrog finite difference method. In the block-LIM, due to duality of voltage and current variables, they are successfully separated from each other by using a staggered time step placement. Thus, each of them can be updated individually within a local block through a time stepping procedure. In this work, we build a reduced order model of the partitioned local block to improve the efficiency of the block-LIM. Compared to other circuit partitioning techniques coupled with the MOR, the order-reduced block-LIM can easily decrease whole computational costs of the transient simulation. Numerical results show that our approach is adequate for the fast simulation of tightly coupled multiconductor transmission lines with CMOS inverters. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | block latency insertion method / CMOS inverter / fast circuit simulation / model order reduction |
| Paper # | CAS2011-41,NLP2011-68 |
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| Committee | CAS |
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| Conference Date | 2011/10/13(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fast Simulation of Multiconductor System with Nonlinear Devices by Using Block-Latency Insertion Method and Reduced Order Model |
| Sub Title (in English) | |
| Keyword(1) | block latency insertion method |
| Keyword(2) | CMOS inverter |
| Keyword(3) | fast circuit simulation |
| Keyword(4) | model order reduction |
| 1st Author's Name | Tadatoshi SEKINE |
| 1st Author's Affiliation | Dept. of Information Science and Tech., Graduate School of Science and Tech., Shizuoka University() |
| 2nd Author's Name | Hideki ASAI |
| 2nd Author's Affiliation | Dept. of Systems Eng., Shizuoka University:Dept. of Information Science and Tech., Graduate School of Science and Tech., Shizuoka University |
| Date | 2011-10-20 |
| Paper # | CAS2011-41,NLP2011-68 |
| Volume (vol) | vol.111 |
| Number (no) | 242 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |