| Presentation | 2011-09-27 Performance Comparison of the Pattern-Recognition Hardware Using Data-Direct-Implementation Approach Yusuke SATO, Moritoshi YASUNAGA, Noriyuki AIBE, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have proposed a novel architecture called "Direct Data Implementation (DDI)" aiming for a super high-speed recognition system. DDI is composed of dedicated circuits that have the same parallelism as the number of sample patterns by embedding known patterns directly to logic circuits. In this paper, we evaluated the power consumption, processing speed and circuit size of DDI implemented in the FPGAs on the prototype board made in the latest report. As a result, we have measured that DDI requires about 1/74 times less energy, 120 times higher processing speed and about 1.4 times larger circuit size than the traditional parallel pattern recognition circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Pattern Recognition / Parallel Processing / Power Consumption / Circuit Size / Processing Speed |
| Paper # | RECONF2011-39 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2011/9/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Comparison of the Pattern-Recognition Hardware Using Data-Direct-Implementation Approach |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Pattern Recognition |
| Keyword(3) | Parallel Processing |
| Keyword(4) | Power Consumption |
| Keyword(5) | Circuit Size |
| Keyword(6) | Processing Speed |
| 1st Author's Name | Yusuke SATO |
| 1st Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba() |
| 2nd Author's Name | Moritoshi YASUNAGA |
| 2nd Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba |
| 3rd Author's Name | Noriyuki AIBE |
| 3rd Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba |
| Date | 2011-09-27 |
| Paper # | RECONF2011-39 |
| Volume (vol) | vol.111 |
| Number (no) | 218 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |