| Presentation | 2011-09-27 Design and Implementation of Adaptive Viterbi Decoder Using Dynamic Reconfigurable System STP Engine Yuken KISHIMOTO, Takao TOI, Takaaki MIYAJIMA, Hideharu AMANO, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Implementing Viterbi Algorithm that is the decoding method of Convolutional code on hard-wired logic, in order to various decode conditon by changing the constraint length or decode precisions, dedicated hardware circuits for each condition are required and switched resulting extra cost and consuming power. Although this redundant hardware can be omitted by replacing the hard-wired logic on FPGA (Field Programmable Gate Array), the time for loading configuration data often takes milliseconds and causes too long system stall. In this paper, we implemented the Viterbi algorithm whose constraint length are from 3 to 7 on Dynamic Reconfigurable System STP Engine and replaced them according to the condition. A certain threshold of BER (Bit Error Rate) is set for a fixed SNR (Signal Noise Rate) and Viterbi decoder with multiple constraint lengths is simulated. In the result of evalutation when the at least 5.07Mbps thorough put is eusured even with frequent recofiguration was performed, the thorough put is improved by 10-140% compared with the case when a constraint length of the best performance is only utilized. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable Processor / Viterbi Decode / Software-Defined Radio |
| Paper # | RECONF2011-38 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2011/9/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation of Adaptive Viterbi Decoder Using Dynamic Reconfigurable System STP Engine |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable Processor |
| Keyword(2) | Viterbi Decode |
| Keyword(3) | Software-Defined Radio |
| 1st Author's Name | Yuken KISHIMOTO |
| 1st Author's Affiliation | Faculity of Science and Technology, Keio University() |
| 2nd Author's Name | Takao TOI |
| 2nd Author's Affiliation | Faculity of Science and Technology, Keio University |
| 3rd Author's Name | Takaaki MIYAJIMA |
| 3rd Author's Affiliation | Faculity of Science and Technology, Keio University |
| 4th Author's Name | Hideharu AMANO |
| 4th Author's Affiliation | Faculity of Science and Technology, Keio University |
| Date | 2011-09-27 |
| Paper # | RECONF2011-38 |
| Volume (vol) | vol.111 |
| Number (no) | 218 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |