Presentation 2011-09-27
Parallel template matching operations on a dynamically reconfigurable vision-chip architecture
Yuichiro YAMAJI, Hironari NAKADA, Minoru WATANABE, Shoji KAWAHITO,
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Abstract(in English) Recently, development of a high-speed image processing system is required for autonomous robots and cars, and so on. Up to now, some vision chips including processing elements have been developed. However, such vision chip can only execute simple operations and its performance is insufficient to execute real-time image recognition operations. Therefore, we have been developing a dynamically reconfigurable vision-chip architecture. This paper presents the experimental results of 4-point parallel template matching operations on a dynamically reconfigurable vision-chip architecture.
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Keyword(in English) Optically Reconfigurable Gate Arrays (ORGAs) / Hologram / Dynamic reconfiguration / Vision chip
Paper # RECONF2011-35
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Committee RECONF
Conference Date 2011/9/19(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Parallel template matching operations on a dynamically reconfigurable vision-chip architecture
Sub Title (in English)
Keyword(1) Optically Reconfigurable Gate Arrays (ORGAs)
Keyword(2) Hologram
Keyword(3) Dynamic reconfiguration
Keyword(4) Vision chip
1st Author's Name Yuichiro YAMAJI
1st Author's Affiliation Faculty of Engineering, Shizuoka University()
2nd Author's Name Hironari NAKADA
2nd Author's Affiliation Primearth EV Energy Co., Ltd.
3rd Author's Name Minoru WATANABE
3rd Author's Affiliation Faculty of Engineering, Shizuoka University
4th Author's Name Shoji KAWAHITO
4th Author's Affiliation Research Institute of Electronics, Shizuoka University
Date 2011-09-27
Paper # RECONF2011-35
Volume (vol) vol.111
Number (no) 218
Page pp.pp.-
#Pages 5
Date of Issue