Presentation 2011-09-27
A Design Framework for relieving a HW Bottleneck on FPGAs Connected with a High-Speed Data Bus
Koichi ARAKI, Yukinori SATO, Yasushi IGUCHI,
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Abstract(in English) As reconfigurable devices with a PCI-Express interface appear in the market, the data transter speed between the reconfigurable devices and other units increases. However, if the Hardware execution time is longer than the data transfer time, the data transfer is suspended to wait the hardware execution. In this paper, we propose a novel framework for implementing hardware structure which can process a data parallel loop using an reconfigurable device without suspending the data transfer. As a result of performance evaluation, we show that hardware generated by the our framework performs well in terms of the hi-speed data transfer and the the hardware execution on an FPGA.
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Keyword(in English) PCI Express / Data Parallelism / Data Transfer
Paper # RECONF2011-33
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Committee RECONF
Conference Date 2011/9/19(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Design Framework for relieving a HW Bottleneck on FPGAs Connected with a High-Speed Data Bus
Sub Title (in English)
Keyword(1) PCI Express
Keyword(2) Data Parallelism
Keyword(3) Data Transfer
1st Author's Name Koichi ARAKI
1st Author's Affiliation School of Infomation Science Japan Advanced Institute of Science and Technology()
2nd Author's Name Yukinori SATO
2nd Author's Affiliation Research Center for Advanced Computing Infrastructure Japan Advanced Institute of Science and Technology
3rd Author's Name Yasushi IGUCHI
3rd Author's Affiliation Research Center for Advanced Computing Infrastructure Japan Advanced Institute of Science and Technology
Date 2011-09-27
Paper # RECONF2011-33
Volume (vol) vol.111
Number (no) 218
Page pp.pp.-
#Pages 6
Date of Issue