| Presentation | 2011-09-26 Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs : Hardware and Reconfiguration Layers Krzysztof Jozwik, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Preemption techniques for HW (hardware) tasks have been studied in order to improve their responsiveness and to allow implementation of a blocking call within a task. In order to support preemption of HW tasks at a level of a conventional software multitasking OS, context saving and restoring mechanisms must be implemented in hardware and appropriate software programming interface, abstracting their implementation details, provided. This paper presents a solution for efficient preemptive hardware multitasking on Xilinx Virtex FPGAs. It comprises an embedded system framework and design flow back-end tools which automate generation of preemptable HW tasks and configuration files used by the framework. The framework features in a high-speed reconfiguration/readback controller and a low-footprint configuration layer. The layer provides an easy-to-use API (Application Programming Interface) facilitating management of the preemption process, which could be used as a base of a fully fledged preemptive SW/HW multitasking OS. The framework has been implemented on top of the Virtex-4 FPGAs and showed promising results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Run-time Reconfiguration / Dynamic Reconfiguration / FPGA |
| Paper # | RECONF2011-29 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2011/9/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs : Hardware and Reconfiguration Layers |
| Sub Title (in English) | |
| Keyword(1) | Run-time Reconfiguration |
| Keyword(2) | Dynamic Reconfiguration |
| Keyword(3) | FPGA |
| 1st Author's Name | Krzysztof Jozwik |
| 1st Author's Affiliation | Graduate School of Information Science, Nagoya University() |
| 2nd Author's Name | Shinya Honda |
| 2nd Author's Affiliation | Graduate School of Information Science, Nagoya University |
| 3rd Author's Name | Hiroyuki Tomiyama |
| 3rd Author's Affiliation | Graduate School of Information Science, Nagoya University |
| 4th Author's Name | Hiroaki Takada |
| 4th Author's Affiliation | College of Science and Engineering, Ritsumeikan University |
| Date | 2011-09-26 |
| Paper # | RECONF2011-29 |
| Volume (vol) | vol.111 |
| Number (no) | 218 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |