Presentation 2011-09-26
Development Modeling Compiler and Operation Test for the Hardware Design Generate HDL from UML State Machine Diagram
Daiki KANO, Ryota YAMAZAKI, Naohiko SHIMIZU,
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Abstract(in English) This paper describes the UML modeling compiler and operation test using that. The UML modeling compiler performs automatic creation of the hardware description language which can be logic synthesis using the UML class diagrams and the UML activity diagrams and the UML state machine diagrams, and it performs hard- ware design all with the system level. We show the rule to make the UML state machine diagram correspond to the NSL language. In this rule, we developed UML modeling compiler STA2NSL which generates NSL detail from state machine diagram. We detail operation state of hardware to UML state machine diagram. We designed hardware which needs state transition using this way, and we verify to operate truly.
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Keyword(in English) UML / Class Diagram / Activity Diagram / State Machine Diagram / Hardware Design / FPGA
Paper # RECONF2011-27
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Committee RECONF
Conference Date 2011/9/19(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development Modeling Compiler and Operation Test for the Hardware Design Generate HDL from UML State Machine Diagram
Sub Title (in English)
Keyword(1) UML
Keyword(2) Class Diagram
Keyword(3) Activity Diagram
Keyword(4) State Machine Diagram
Keyword(5) Hardware Design
Keyword(6) FPGA
1st Author's Name Daiki KANO
1st Author's Affiliation Tokai University()
2nd Author's Name Ryota YAMAZAKI
2nd Author's Affiliation Tokai University
3rd Author's Name Naohiko SHIMIZU
3rd Author's Affiliation Tokai University
Date 2011-09-26
Paper # RECONF2011-27
Volume (vol) vol.111
Number (no) 218
Page pp.pp.-
#Pages 6
Date of Issue