Presentation	2011-09-26 Low Power Dynamically Reconfigurable Processor with Dual-Vdd/Dual-Vth and tis Optimization Kazuei HIRONAKA, Hideharu AMANO,
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Abstract(in English)	Increasing the number of functions in the mobile devices requires high perfomance architectures with low power consumption. Coarse-grained dynamically reconfigurable processor (CGDRP) is received an attetion as a way to fulfil these requirements. Here, we propose a CGDRP architecture with DualVdd/DualVth low-power techniques, and evaluate to find the most efficient Vdd and Vth assignment for target applications.
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Keyword(in English)	Dynamically Reconfigurable System / Low Power Design / Placement and Route
Paper #	RECONF2011-24
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Committee	RECONF
Conference Date	2011/9/19(1days)
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Paper Information
Registration To	Reconfigurable Systems (RECONF)
Language	JPN
Title (in Japanese)	(See Japanese page)
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Title (in English)	Low Power Dynamically Reconfigurable Processor with Dual-Vdd/Dual-Vth and tis Optimization
Sub Title (in English)
Keyword(1)	Dynamically Reconfigurable System
Keyword(2)	Low Power Design
Keyword(3)	Placement and Route
1st Author's Name	Kazuei HIRONAKA
1st Author's Affiliation	Faculty of science and Technology, Keio University()
2nd Author's Name	Hideharu AMANO
2nd Author's Affiliation	Faculty of science and Technology, Keio University
Date	2011-09-26
Paper #	RECONF2011-24
Volume (vol)	vol.111
Number (no)	218
Page	pp.pp.-
#Pages	6
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