| Presentation | 2011-09-26 Feasibility study of Nonvolatile Reconfigurable Device by using a Standerd CMOS logic process Shuji KUNIMITSU, Mamoru TERAUCHI, Kazuya TANIGAWA, Tetsuo HIRONAKA, Masayuki SATO, Takashi ISHIGURO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we consider the realization of nonvolatile PLD, based on the new reconfigurable device architecture MPLD. MPLD (Memory based PLD) realize LUT and switch function equivalent in FPGA by using MLUT ( Multi-directional Look Up Tables) as its fundamental element. In the conventional implementation SRAM cell arrays are used in implementing MLUTs. In this paper, we replace the SRAM cell with nonvolatile memory cells to implement the nonvolatile MPLD. In that case, simply replacing the memory cell arrays are not enough to implement non-volatile MPLD. This is because MPLD requires asynchronous memory read operations on logic mode, and high voltages on writing the non-volatile memory cell arrays. Moreover, there is a problem that the cost goes up by using a flash memory process. So we considered designing the MLUT by using a nonvolatile memory that is possible to manufacture in the standard CMOS logic process, and designed the control circuits for it. Prom the simulation result, we confirmed MPLD with a nonvolatile characteristic can function as a normal MPLD. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MPLD / memory / nonvolatile / standard logic process / simulation |
| Paper # | RECONF2011-23 |
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| Committee | RECONF |
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| Conference Date | 2011/9/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Feasibility study of Nonvolatile Reconfigurable Device by using a Standerd CMOS logic process |
| Sub Title (in English) | |
| Keyword(1) | MPLD |
| Keyword(2) | memory |
| Keyword(3) | nonvolatile |
| Keyword(4) | standard logic process |
| Keyword(5) | simulation |
| 1st Author's Name | Shuji KUNIMITSU |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Mamoru TERAUCHI |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Kazuya TANIGAWA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 4th Author's Name | Tetsuo HIRONAKA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 5th Author's Name | Masayuki SATO |
| 5th Author's Affiliation | Taiyo Yuden Co., Ltd |
| 6th Author's Name | Takashi ISHIGURO |
| 6th Author's Affiliation | Taiyo Yuden Co., Ltd |
| Date | 2011-09-26 |
| Paper # | RECONF2011-23 |
| Volume (vol) | vol.111 |
| Number (no) | 218 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |