Presentation	2011/8/18 Status and Prospect of Ultra Low Power Logic Devices Jiro Ida,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Ultra Low Power Application of Sensor network, or, implanted medical devices where battery less, ultimately, is needed, will be in reality with expanding research of energy harvestings. Re-consideration of device specification on logic transistor in VLSI for those applications reveals again the need of reduction of the off current and the subthreshold swing of the transistors. For those applications, status of Bulk transistor, FD-SOI transistor and the super steep cut off transistor which S-value is over the theoretical limit and which research papers are increased, are reviewed. Finally, some data of the steep S-value obtained by floating body effect in SOI transistor which is one of I-MOS are introduced.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Ultra Low Power / Senser Network / FD-SOI / Tunnel FET / Impact Ionization MOS
Paper #	ICD2011-54,SDM2011-86
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Conference Information
Committee	ICD
Conference Date	2011/8/18(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Status and Prospect of Ultra Low Power Logic Devices
Sub Title (in English)
Keyword(1)	Ultra Low Power
Keyword(2)	Senser Network
Keyword(3)	FD-SOI
Keyword(4)	Tunnel FET
Keyword(5)	Impact Ionization MOS
1st Author's Name	Jiro Ida
1st Author's Affiliation	Department of Electrical and Electronic Engineering, College of Engineering Kanazawa Institute of Technology()
Date	2011/8/18
Paper #	ICD2011-54,SDM2011-86
Volume (vol)	vol.111
Number (no)	188
Page	pp.pp.-
#Pages	5
Date of Issue