| Presentation | 2011/8/18 Study of pattern area for reconfigurable logic circuit with DG/CNT transistor Takamichi HAYASHI, Shigeyoshi WATANABE, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Pattern area for 2～6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and Carbon-Nano-Tube (DG and CNT) has been newly estimated. Pattern area and number of logic dependence on input number of logic circuit has been analyzed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MOS double gate transistor / CNT transistor / reconfigurable logic / logic circuit / pattern area |
| Paper # | ICD2011-41,SDM2011-73 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2011/8/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study of pattern area for reconfigurable logic circuit with DG/CNT transistor |
| Sub Title (in English) | |
| Keyword(1) | MOS double gate transistor |
| Keyword(2) | CNT transistor |
| Keyword(3) | reconfigurable logic |
| Keyword(4) | logic circuit |
| Keyword(5) | pattern area |
| 1st Author's Name | Takamichi HAYASHI |
| 1st Author's Affiliation | Department of Engineering Research, Shonan Institute of Technology() |
| 2nd Author's Name | Shigeyoshi WATANABE |
| 2nd Author's Affiliation | Department of Information Science, Shonan Institute of Technology |
| Date | 2011/8/18 |
| Paper # | ICD2011-41,SDM2011-73 |
| Volume (vol) | vol.111 |
| Number (no) | 188 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |