Presentation	2011/8/18 Study of pattern area reduction for standard cell with planar and SGT transistor Takahiro KODAMA, Shigeyoshi WATANABE,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	The pattern area of logic circuit such as inverter and 1bit full adder with SGT (Surrounding Gate Transistor) are compared with that with planar transistor. With using smaller design rule between contact to gate on the active area and thinner gate electrode thickness the pattern area of these circuits with SGT can be reduced drastically compared with that using planar transistor.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	SGT / system LSI / design rule / pattern area / standard cell
Paper #	ICD2011-40,SDM2011-72
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Conference Information
Committee	ICD
Conference Date	2011/8/18(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Study of pattern area reduction for standard cell with planar and SGT transistor
Sub Title (in English)
Keyword(1)	SGT
Keyword(2)	system LSI
Keyword(3)	design rule
Keyword(4)	pattern area
Keyword(5)	standard cell
1st Author's Name	Takahiro KODAMA
1st Author's Affiliation	Department of Information Science, Shonan Institute of Technology()
2nd Author's Name	Shigeyoshi WATANABE
2nd Author's Affiliation	Department of Information Science, Shonan Institute of Technology
Date	2011/8/18
Paper #	ICD2011-40,SDM2011-72
Volume (vol)	vol.111
Number (no)	188
Page	pp.pp.-
#Pages	6
Date of Issue