| Presentation | 2011-08-10 Evaluation of interface state density of Ge-MIS structure by combination of conductance technique at low temperature and room temperature Takuro IWASAKI, Shinya SATO, Soichiro SUZUKI, Toshiro ONO, Yukio FUKUDA, Hiroshi OKAMOTO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Ge-MIS structures have attracted the attention for next generation device, which may take the place of Si-MOS devices. However, further improvement of the interface quality is desired for the Ge-MIS structure. We have reported that the Ge-MIS structure with low interface state density can be made by ECR (Electron Cyclotron Resonance) plasma technique, and that the interface state density of Ge-MIS structure can be evaluated by the characteristic analysis in the inversion region even at room temperature. In this report, we evaluated the interface state density of Ge-MIS structure by combination of conductance technique at low temperature and the characteristic analysis at room temperature. We have successfully obtained the interface state density in the upper half and the lower half of the band gap. The measured interface state density near the middle of the band gap is in a level of 1×10^<11>cm^<-2>eV^<-1>, which is a excellent value for p-type Ge-MIS structure. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ge / Ge-MIS / MIS / Interface State / Conductance Technique |
| Paper # | CPM2011-64 |
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| Committee | CPM |
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| Conference Date | 2011/8/3(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of interface state density of Ge-MIS structure by combination of conductance technique at low temperature and room temperature |
| Sub Title (in English) | |
| Keyword(1) | Ge |
| Keyword(2) | Ge-MIS |
| Keyword(3) | MIS |
| Keyword(4) | Interface State |
| Keyword(5) | Conductance Technique |
| 1st Author's Name | Takuro IWASAKI |
| 1st Author's Affiliation | Graduate School of Science and Technology, Hirosaki University() |
| 2nd Author's Name | Shinya SATO |
| 2nd Author's Affiliation | Graduate School of Science and Technology, Hirosaki University |
| 3rd Author's Name | Soichiro SUZUKI |
| 3rd Author's Affiliation | Graduate School of Science and Technology, Hirosaki University |
| 4th Author's Name | Toshiro ONO |
| 4th Author's Affiliation | Graduate School of Science and Technology, Hirosaki University |
| 5th Author's Name | Yukio FUKUDA |
| 5th Author's Affiliation | Tokyo University of Science, Suwa |
| 6th Author's Name | Hiroshi OKAMOTO |
| 6th Author's Affiliation | Graduate School of Science and Technology, Hirosaki University |
| Date | 2011-08-10 |
| Paper # | CPM2011-64 |
| Volume (vol) | vol.111 |
| Number (no) | 176 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |